Processor Architecture and Design - 30-Mark Internal Exam

Code: OCA-502 MJ
Exam date: Tuesday, 25 August 2026
Available slots: 8:00 AM-10:00 AM or 7:00 PM-9:00 PM
Total questions: 23
Total marks: 30

Instructions

• Answer all questions.
• For multiple-answer MCQs, select every correct option.
• For assertion questions, choose the correct assertion-reason option.
• Time suggested: 90 minutes.

Section 1 - Single-Answer MCQs

4 questions x 1 mark = 4 marks

1. Which register holds the address of the next instruction?

   • A. IR
   • B. PC
   • C. MAR
   • D. ALU

2. Which component translates virtual addresses into physical addresses?

   • A. MMU
   • B. ALU
   • C. Control unit
   • D. Cache controller

3. Which memory is normally the fastest?

   • A. HDD
   • B. DRAM
   • C. Registers
   • D. Optical disk

4. Which event is normally asynchronous?

   • A. Hardware interrupt
   • B. Instruction decode
   • C. Divide-by-zero exception
   • D. System-call trap

Section 2 - Multiple-Answer MCQs

4 questions x 1 mark = 4 marks

5. Which are parts of the CPU datapath? Select all correct answers.

   • A. ALU
   • B. Registers
   • C. Multiplexers
   • D. Hard disk

6. Which are cache miss types? Select all correct answers.

   • A. Compulsory
   • B. Capacity
   • C. Conflict
   • D. Arithmetic

7. Which are benefits of virtual memory? Select all correct answers.

   • A. Process isolation
   • B. Shared page mapping
   • C. Running programs larger than physical RAM
   • D. Guaranteed faster disk access

8. Which statements describe RISC-style design? Select all correct answers.

   • A. Simple instructions
   • B. Load-store operation
   • C. Often fixed-length instructions
   • D. Every instruction directly accesses memory

Section 3 - True/False

4 questions x 1 mark = 4 marks

9. The data bus is usually bidirectional.
10. DRAM requires periodic refresh.
11. A TLB stores complete program instructions.
12. A system call is commonly implemented as a software trap into kernel mode.

Section 4 - Match the Following

1 question x 4 marks = 4 marks

13. Match Column A with Column B.

Column A	Column B
1. PC	a. Translation cache
2. TLB	b. Address of next instruction
3. Kruskal's algorithm	c. Sorts edges and avoids cycles
4. ISR	d. Interrupt service routine

Section 5 - Fill in the Blanks

3 questions x 1 mark = 3 marks

14. The formula for average memory access time is AMAT = __________ + Miss rate x Miss penalty.

15. A page table maps a virtual page number to a physical __________ number.

16. The CPU performs the __________, decode, and execute cycle for each instruction.

Section 6 - Assertion and Reason

3 questions x 1 mark = 3 marks

Use these options:

• A. Both assertion and reason are true, and the reason correctly explains the assertion.
• B. Both assertion and reason are true, but the reason does not explain the assertion.
• C. Assertion is true, but reason is false.
• D. Assertion is false, but reason is true.

17. Assertion: Pipelining improves instruction throughput.
    Reason: Different instructions can occupy different pipeline stages at the same time.

18. Assertion: The ISA and microarchitecture are identical.
    Reason: The ISA defines the software-visible instruction contract, while microarchitecture describes its implementation.

19. Assertion: A page fault is always a fatal error.
    Reason: The operating system can often load a missing page and restart the instruction.

Section 7 - Ordering

3 questions x 1 mark = 3 marks

20. Arrange the instruction cycle: (A) Execute, (B) Fetch, (C) Decode, (D) Write-back.

21. Arrange page-fault handling: (A) Update page table, (B) Detect missing page, (C) Load required page, (D) Restart instruction.

22. Arrange ISR execution: (A) Restore state, (B) Save state, (C) Dispatch handler, (D) Identify and acknowledge source.

Section 8 - Descriptive Question

1 question x 5 marks = 5 marks

23. Explain virtual memory and address translation. Include the roles of virtual pages, physical frames, the MMU, page table, TLB, page fault, and protection bits.

Answer Key

1. B 2. A 3. C 4. A

2. A, B, C 6. A, B, C 7. A, B, C 8. A, B, C

3. True 10. True 11. False 12. True

4. 1-b, 2-a, 3-c, 4-d

5. Hit time 15. frame 16. fetch

6. A 18. D 19. D

7. B, C, A, D 21. B, C, A, D 22. B, D, C, A

Model Answer for Question 23

Virtual memory gives each process a private virtual address space that can be larger than the available physical RAM. The address generated by a program is called a virtual address. It is divided into a virtual page number and an offset. Physical memory is divided into frames of the same size. The page offset does not change during translation; the virtual page number is replaced by the physical frame number.

The Memory Management Unit, or MMU, performs this translation. It first checks the Translation Lookaside Buffer, or TLB, which is a small cache of recent page translations. A TLB hit gives a fast frame number. On a TLB miss, the MMU consults the process's page table in memory and may place the new translation in the TLB.

If the page-table entry says that the required page is not present in RAM, the MMU raises a page fault. The operating system handles the fault by selecting a free or replacement frame, writing back a dirty page if necessary, loading the required page from storage, updating the page table and TLB, and restarting the faulting instruction. A page fault is therefore often a normal recoverable event, although it is slower than a normal memory access.

Page-table protection bits control whether a page is present and whether it may be read, written, or executed. User/supervisor bits prevent user programs from accessing kernel memory, while dirty and accessed bits help page replacement. Virtual memory therefore provides address-space abstraction, process isolation, controlled sharing, and demand paging, with translation and page-fault overhead as its main costs.