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Processor Architecture and Design - Expected Questions
This is a revision-focused expected-question set for the second exam day. It follows the confirmed 30-mark pattern. These are important practice questions, not a guarantee of the exact university paper.
Exam: OCA-502 MJ | Tuesday, 25 August 2026
Slots: 8:00 AM-10:00 AM or 7:00 PM-9:00 PM
Section 1 - Single-Answer MCQs
4 questions x 1 mark = 4 marks
Which unit generates control signals for the datapath?
- A. Control unit
- B. Cache
- C. DRAM
- D. Address bus
Which memory uses capacitor-based storage and requires refresh?
- A. SRAM
- B. DRAM
- C. Register
- D. ROM only
Which structure stores recent virtual-to-physical translations?
- A. TLB
- B. ALU
- C. IR
- D. Stack
Which event is caused by an external device or timer?
- A. Hardware interrupt
- B. Trap
- C. Invalid opcode exception
- D. Decode operation
Section 2 - Multiple-Answer MCQs
4 questions x 1 mark = 4 marks
Which are stages commonly found in a pipeline? Select all correct answers.
- A. Fetch
- B. Decode
- C. Execute
- D. Compile only
Which are responsibilities of the control unit? Select all correct answers.
- A. Generate control signals
- B. Sequence instruction execution
- C. Coordinate register and memory transfers
- D. Perform all arithmetic calculations
Which are benefits of virtual memory? Select all correct answers.
- A. Process isolation
- B. Demand paging
- C. Address-space abstraction
- D. Zero page-fault cost
Which statements describe CISC? Select all correct answers.
- A. Rich instruction set
- B. Complex addressing modes
- C. Often variable-length instructions
- D. Always uses only load and store instructions
Section 3 - True/False
4 questions x 1 mark = 4 marks
- The program counter stores the address of the next instruction.
- SRAM is normally denser and cheaper than DRAM.
- Forwarding can reduce some data-hazard stalls.
- A system call transfers a program directly to unrestricted hardware access without kernel control.
Section 4 - Match the Following
1 question x 4 marks = 4 marks
- Match Column A with Column B.
| Column A | Column B |
|---|---|
| 1. Structural hazard | a. Wrong-path instructions after a branch |
| 2. Data hazard | b. Two operations need the same hardware resource |
| 3. Control hazard | c. Instruction depends on an earlier result |
| 4. Cache miss | d. Data is absent from the requested cache level |
Section 5 - Fill in the Blanks
3 questions x 1 mark = 3 marks
The three main system-bus categories are data, address, and __________.
A recoverable exception caused when a required page is absent from RAM is a __________ fault.
RISC commonly follows a __________-store architecture.
Section 6 - Assertion and Reason
3 questions x 1 mark = 3 marks
Use these options:
- A. Both assertion and reason are true, and the reason correctly explains the assertion.
- B. Both assertion and reason are true, but the reason does not explain the assertion.
- C. Assertion is true, but reason is false.
- D. Assertion is false, but reason is true.
Assertion: A cache improves average memory performance.
Reason: Frequently accessed data can be supplied from a faster memory level.Assertion: A control hazard may occur after a branch instruction.
Reason: The processor may not yet know which instruction address should be fetched next.Assertion: Kernel mode has fewer privileges than user mode.
Reason: Kernel mode is used for protected operations such as memory and device management.
Section 7 - Ordering
3 questions x 1 mark = 3 marks
Arrange the fetch-decode-execute cycle: (A) Execute, (B) Fetch, (C) Decode, (D) Write-back.
Arrange virtual-address translation after a TLB miss: (A) Access physical memory, (B) Generate virtual address, (C) Walk page table, (D) Update/fill TLB.
Arrange interrupt response: (A) Restore saved state, (B) Save processor state, (C) Dispatch through vector, (D) Service and clear interrupt source.
Section 8 - Descriptive Question
1 question x 5 marks = 5 marks
- Explain the difference between an interrupt, exception, and trap. Also explain user mode, kernel mode, interrupt vector, and the main steps of an interrupt service routine.
Answer Key
A 2. B 3. A 4. A
A, B, C 6. A, B, C 7. A, B, C 8. A, B, C
True 10. False 11. True 12. False
1-b, 2-c, 3-a, 4-d
control 15. page 16. load
A 18. A 19. D
B, C, A, D 21. B, C, D, A 22. B, C, D, A
Model Answer for Question 23
An interrupt is an asynchronous event generated by an external device or timer, such as a keyboard, disk, or clock. It is not directly tied to the instruction currently executing. An exception is a synchronous event caused by the current instruction, such as divide-by-zero, invalid opcode, or a page fault. A trap is a deliberate synchronous software event, commonly produced by a system-call instruction when a user program requests an operating-system service.
The processor separates user mode and kernel mode for protection. User mode allows ordinary applications to execute restricted instructions and access their permitted memory. Kernel mode gives the operating system privileged access to hardware, page tables, devices, and protected memory. A system call or interrupt transfers controlled execution to kernel mode; the program does not receive unrestricted hardware access.
An interrupt vector is a table that maps an interrupt or exception number to the address of its handler. When an event occurs, the processor saves important state such as the program counter and status register, changes privilege mode if required, identifies the vector, and jumps to the appropriate interrupt service routine.
The ISR saves any additional registers it will modify, identifies and acknowledges the source, performs short urgent work, clears the device's interrupt condition, and may schedule deferred work for the operating system. Finally, it restores the saved state and executes a return-from-interrupt instruction. The interrupted program can then continue. ISRs should be short, careful, and non-blocking because they run in a privileged context and delay other work while active.