Processor Architecture and Design - Practice Test 1

Section A - Short Objective Questions

1. Define stored-program concept.
2. What is the role of the control unit?
3. Name the three types of buses in a computer system.
4. What is a cache hit?
5. Expand ISA.
6. What is a hazard in pipelining?

Section B - Short Problems

7. State the AMAT formula.
8. Differentiate SRAM and DRAM in one line each.
9. List any four components of the CPU or system unit.

Section C - Long Answer

10. Explain the instruction cycle and the role of the PC.
11. Compare RISC and CISC.

Answer Key

1. Instructions and data are stored in the same memory.
2. It generates control signals and sequences execution.
3. Data bus, address bus, control bus.
4. Data is found in cache.
5. Instruction Set Architecture.
6. A condition that prevents ideal pipeline flow, such as structural, data, or control conflict.
7. AMAT = Hit time + Miss rate x Miss penalty
8. SRAM is faster and no refresh; DRAM is slower and needs refresh.
9. Any four: CPU, memory, I/O devices, buses, chipset, registers, ALU, control unit.
10. Fetch, decode, execute, write-back; PC points to the next instruction and updates as instructions complete.
11. RISC uses simple, fixed instructions and load-store design; CISC uses more complex instructions and richer addressing modes.